The present invention relates generally to a method of fabricating an integrated circuit (IC) and more specifically to a method of fabricating an IC having dual threshold voltage capability.
In very large-scale integrated circuits (VLSI), and even more so in ultra large-scale integrated (ULSI) circuits, it is desirable to design and fabricate MOSFET devices with different threshold voltages on the same integrated circuit (IC). By allowing MOSFET devices with differing threshold voltages, IC performance can be improved without unnecessarily increasing power dissipation. For example, in a speed critical signal path, MOSFET devices with low threshold voltages can be used. A MOSFET with a low threshold voltage has an increased drive current and thus, an increased transistor switching speed. Alternatively, in a non-critical signal path where circuit speed is less important, MOSFET devices with high threshold voltages can be used. A MOSFET with a high threshold voltage exhibits reduced leakage current and thus, reduced standby power dissipation.
The ability to decrease power dissipation while increasing IC performance is critical in many applications involving ICs. In some applications, it is common for IC devices to be continually powered. For example, in a personal computer (PC) it is desirable to leave the machine operational to avoid time wasted booting the machine. In a PC, it is desirable to have very low power dissipation when the machine is powered, but not in use. But, when he machine is in use, increased circuit performance is desirable.
A notebook computer provides another application of ICs including dual threshold voltage MOSFET devices. In the optimal notebook computer, it is desirable to achieve a high circuit performance and yet maintain extended battery life. By using ICs with dual threshold voltages, the IC performance can be increased while avoiding unnecessary increase in power dissipation and a corresponding degradation in battery life.
In the conventional CMOS process, dual threshold voltages are realized by implanting transistor active areas with differing levels of dopant density (e.g. different dopant dose). For example, for transistor active areas where a low threshold voltage is desired, a regular dopant density is implanted into the channel region (a regular channel implant). In other active areas, where a high threshold voltage is required, an additional implant is performed to increase dopant density in the channel area (an additional channel implant).
While the conventional method provides transistors with dual threshold voltages, the method has a negative impact on IC yield and manufacturability. Most notably, as short-channel effects are determined by the channel implant dopant concentration, the conventional method can adversely impacts short-channel effects within the IC. By having different levels of dopant concentration in different active areas, short-channel effects vary from one active area to another across the wafer. This variance in short-channel performance makes IC fabrication more difficult and less predictable.
Accordingly, there is a need for an improved method of fabricating dual threshold voltage IC devices. Further, there is a need for a method which allows for multiple threshold voltage IC devices that does not result in varying short-channel effects across the IC. Further still, there is a need for a method of fabricating an integrated circuit having dual threshold voltage IC devices without utilizing conventional channel implants.
According to one embodiment, a method provides voltage adjustment between two regions of a device. The device includes a channel region between the two regions. The method includes providing a semiconductor substrate and providing an inert material into the semiconductor substrate. The inert material accumulates below the channel region and confines a depletion layer dimension during operation of the device.
According to another embodiment, a method of fabricating an integrated circuit is provided. The integrated circuit includes voltage threshold adjustment between two regions of a device. In this embodiment, the device includes a channel region between the two regions. The method includes providing a semiconductor substrate, forming a gate on the substrate near the channel region, and implanting an inert implant material through the gate so that the inert implant material accumulates beneath the channel region within the substrate. Advantageously, the accumulation of implant material confines a depletion layer dimension during operation of the device.
According to another embodiment, an integrated circuit device having voltage threshold adjustment is provided between two regions of the device. The device includes a channel region between the two regions. Further, the device comprises a semiconductor substrate and an accumulation of inert material below the channel region. Advantageously, the accumulation of inert material confines a depletion layer dimension during operation of the device.
According to yet another embodiment, a transistor having a gate, channel region, source and drain is disclosed. The gate is disposed over the channel region which is formed between the source and drain. The transistor includes an accumulation of inert ions formed below the channel region. Advantageously, the accumulation of inert ions provides a semi-insulative layer below the channel region, which acts to prevent the channel from extending deeper in a vertical direction during operation of the transistor.